723 search results - page 103 / 145 » Speculative Dynamic Vectorization |
84
Voted
ITC
2000
IEEE
15 years 6 months ago
2000
IEEE
The use of a single pass/fail threshold for IDDQ testing is unworkable as chip background currents increase to the point where they exceed many defect currents. This paper describ...
129
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DATE
1999
IEEE
15 years 6 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
99
Voted
ICCAD
1998
IEEE
15 years 6 months ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
121
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CPE
1998
Springer
15 years 6 months ago
1998
Springer
We present a new dynamic probabilistic state exploration algorithm based on hash compaction. Our method has a low state omission probability and low memory usage that is independen...
EUROPAR
1995
Springer
15 years 5 months ago
1995
Springer
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance ga...