Sciweavers

723 search results - page 15 / 145
» Speculative Dynamic Vectorization
Sort
View
ICCD
2003
IEEE
104views Hardware» more  ICCD 2003»
15 years 10 months ago
On Reducing Register Pressure and Energy in Multiple-Banked Register Files
The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. In this paper, we present a novel technique to reduce ...
Jaume Abella, Antonio González
MICRO
2010
IEEE
175views Hardware» more  MICRO 2010»
14 years 11 months ago
Efficient Selection of Vector Instructions Using Dynamic Programming
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar
ISCA
1999
IEEE
87views Hardware» more  ISCA 1999»
15 years 6 months ago
Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs
Several ILP limit studies indicate the presence of considerable ILP across dynamically far-apart instructions in program execution. This paper proposes a hardware mechanism, dynam...
Sriram Vajapeyam, P. J. Joseph, Tulika Mitra
123
Voted
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 6 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
COLING
2002
15 years 1 months ago
Word Sense Disambiguation using Static and Dynamic Sense Vectors
It is popular in WSD to use contextual information in training sense tagged data. Co-occurring words within a limited window-sized context support one sense among the semantically...
Jong-Hoon Oh, Key-Sun Choi