One of the main concerns in today's processor design is the issue logic. Instruction-level parallelism is usually favored by an out-of-order issue mechanism where instruction...
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs th...
We present a novel approach to knowledge-based automated oneshot multi-issue bilateral negotiation handling, in a homogeneous setting, both numerical features and non-numerical on...
Azzurra Ragone, Tommaso Di Noia, Eugenio Di Sciasc...
We propose a framework for multi-issue bilateral negotiation, where issues are expressed and related to each other via Description Logics. Agents’ goals are expressed through (c...
Azzurra Ragone, Tommaso Di Noia, Eugenio Di Sciasc...