122 search results - page 10 / 25 » Speculative Parallel Threading Architecture and Compilation |
112
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IWMM
2010
Springer
15 years 4 months ago
2010
Springer
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
101
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HPCA
2001
IEEE
16 years 1 days ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
ICCD
2002
IEEE
15 years 8 months ago
2002
IEEE
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
MICRO
1998
IEEE
15 years 3 months ago
1998
IEEE
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
LCPC
2004
Springer
15 years 5 months ago
2004
Springer
Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor a...