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TCAD
2008
112views more  TCAD 2008»
14 years 11 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
75
Voted
IPPS
2000
IEEE
15 years 3 months ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
DAC
2001
ACM
16 years 1 days ago
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors
We present a methodology for microarchitectural customization of embedded processors by exploiting application information, thus attaining the twin benefits of processor standardi...
Peter Petrov, Alex Orailoglu
ICML
2006
IEEE
15 years 12 months ago
Concept boundary detection for speeding up SVMs
Support Vector Machines (SVMs) suffer from an O(n2 ) training cost, where n denotes the number of training instances. In this paper, we propose an algorithm to select boundary ins...
Navneet Panda, Edward Y. Chang, Gang Wu
WWW
2008
ACM
15 years 11 months ago
Speeding up web service composition with volatile external information
This paper introduces a novel method for composing Web services in the presence of external volatile information. Our approach, which we call the informed-presumptive, is compared...
John Harney, Prashant Doshi