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» Speeding up model checking by exploiting explicit and hidden...
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63
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DATE
2009
IEEE
101views Hardware» more  DATE 2009»
15 years 5 months ago
Speeding up model checking by exploiting explicit and hidden verification constraints
Gianpiero Cabodi, Paolo Camurati, Luz Garcia, Marc...
82
Voted
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
15 years 10 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
82
Voted
DAC
2008
ACM
15 years 11 months ago
Faster symmetry discovery using sparsity of symmetries
Many computational tools have recently begun to benefit from the use of the symmetry inherent in the tasks they solve, and use general-purpose graph symmetry tools to uncover this...
Paul T. Darga, Karem A. Sakallah, Igor L. Markov