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» Sphere Decoding for Multiprocessor Architectures
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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
13 years 11 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
FPL
2007
Springer
137views Hardware» more  FPL 2007»
14 years 13 days ago
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA
Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and progr...
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesm...
ESTIMEDIA
2004
Springer
13 years 11 months ago
Application design trajectory towards reusable coprocessors MPEG case study
This paper presents a structured application design trajectory to transform media-processing applications— modeled as Kahn process network—into a set of functionspecific hardw...
Martijn J. Rutten, Om Prakash Gangwal, Jos T. J. v...
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
13 years 12 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ESTIMEDIA
2004
Springer
13 years 11 months ago
A queuing-theoretic performance model for context-flow system-on-chip platforms
Abstract—Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which pre...
Rami Beidas, Jianwen Zhu