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120
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ASPDAC
2005
ACM
101views Hardware» more  ASPDAC 2005»
15 years 5 months ago
A wideband hierarchical circuit reduction for massively coupled interconnects
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
110
Voted
HIPEAC
2010
Springer
15 years 5 months ago
Offload - Automating Code Migration to Heterogeneous Multicore Systems
We present Offload, a programming model for offloading parts of a C++ application to run on accelerator cores in a heterogeneous multicore system. Code to be offloaded is enclosed ...
Pete Cooper, Uwe Dolinsky, Alastair F. Donaldson, ...
124
Voted
DAC
2005
ACM
15 years 5 months ago
VLIW: a case study of parallelism verification
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Li...
147
Voted
ECAI
2008
Springer
15 years 5 months ago
Optimizing Causal Link Based Web Service Composition
Automation of Web service composition is one of the most interesting challenges facing the Semantic Web today. Since Web services have been enhanced with formal semantic descriptio...
Freddy Lécué, Alexandre Delteil, Ala...
140
Voted
NETWORKING
2007
15 years 5 months ago
Optimal Topology Design for Overlay Networks
Abstract. The topology creation is one of the most important step for the design of an overlay network. Traffic characteristic and volume, and behavior of nodes which can be sel...
Mina Kamel, Caterina M. Scoglio, Todd Easton