157 search results - page 24 / 32 » Staircase-down SET programming approach for phase-change mem... |
132
click to vote
IWOMP
2007
Springer
15 years 6 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
104
click to vote
CCGRID
2002
IEEE
15 years 4 months ago
2002
IEEE
Despite the large research efforts in the SW–DSM community, this technology has not yet been adapted widely for significant codes beyond benchmark suites. One of the reasons co...
DFT
2003
IEEE
15 years 5 months ago
2003
IEEE
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
114
click to vote
ISCA
1991
IEEE
15 years 3 months ago
1991
IEEE
We use mean value analysis models to compare representative hardware and software cache coherence schemes for a large-scale shared-memory system. Our goal is to identify the workl...
106
click to vote
SCOPES
2004
Springer
15 years 5 months ago
2004
Springer
For mobile embedded systems, the energy consumption is a limiting factor because of today’s battery capacities. Besides the processor, memory accesses consume a high amount of en...