Sciweavers

157 search results - page 6 / 32
» Staircase-down SET programming approach for phase-change mem...
Sort
View
CASES
2010
ACM
14 years 7 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
82
Voted
ASAP
2004
IEEE
119views Hardware» more  ASAP 2004»
15 years 1 months ago
Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators
Distributed local memories, or scratchpads, have been shown to effectively reduce cost and power consumption of application-specific accelerators while maintaining performance. Th...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott...
CAV
2009
Springer
177views Hardware» more  CAV 2009»
15 years 10 months ago
Software Transactional Memory on Relaxed Memory Models
Abstract. Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptio...
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
DAC
2004
ACM
15 years 10 months ago
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
Memory-related activity is one of the major sources of energy consumption in embedded systems. Many types of memories used in embedded systems allow multiple operating modes (e.g....
Chun-Gi Lyuh, Taewhan Kim
82
Voted
MICRO
1997
IEEE
82views Hardware» more  MICRO 1997»
15 years 1 months ago
Procedure Based Program Compression
Cost and power consumption are two of the most important design factors for many embedded systems, particularly consumer devices. Products such as Personal Digital Assistants, pag...
Darko Kirovski, Johnson Kin, William H. Mangione-S...