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HPCA
2005
IEEE
15 years 10 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
HPCA
2004
IEEE
15 years 10 months ago
Out-of-Order Commit Processors
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
Adrián Cristal, Daniel Ortega, Josep Llosa,...
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
15 years 3 months ago
SODA: A Low-power Architecture For Software Radio
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scot...
PDP
2007
IEEE
15 years 3 months ago
Improving the Development Process for CSE Software
Scientific and engineering programming has been around since the beginning of computing, often being the driving force for new system development and innovation. At the same time...
Michael A. Heroux, James M. Willenbring, Michael N...
CLOUD
2010
ACM
15 years 2 months ago
Virtual machine power metering and provisioning
Virtualization is often used in cloud computing platforms for its several advantages in efficiently managing resources. However, virtualization raises certain additional challeng...
Aman Kansal, Feng Zhao, Jie Liu, Nupur Kothari, Ar...