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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
15 years 3 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
SRDS
2003
IEEE
15 years 3 months ago
Raptor: Integrating Checkpoints and Thread Migration for Cluster Management
distributed shared-memory (SDSM) provides the abstraction necessary to run shared-memory applications on cost-effective parallel platforms such as clusters of workstations. Howeve...
Hazim Shafi, Evan Speight, John K. Bennett
VRML
1999
ACM
15 years 2 months ago
Avatars in LivingSpace
We describe how we implemented the avatars we use to represent users in LivingSpace, our implementation of the Living Worlds standard for multi-user distributed VRML worlds. Livin...
Mike Wray, Vincent Belrose
IEEEPACT
2007
IEEE
15 years 4 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
ICPP
1995
IEEE
15 years 1 months ago
Progress: A Toolkit for Interactive Program Steering
Interactive program steering permits researchers to monitor and guide their applications during runtime. Interactive steering can help make end users more effective in addressing ...
Jeffrey S. Vetter, Karsten Schwan