Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
Alexandre E. Eichenberger, Edward S. Davidson, San...
This paper describes a scenario-based methodology em-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existi...
We present Beaver, a method and architecture to "build dams" to protect servers from Denial of Service (DoS) attacks. Beaver allows efficient filtering of DoS traffic us...
Gal Badishi, Idit Keidar, Amir Herzberg, Oleg Roma...
Most existing tools for the synthesisof asynchronouscircuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper ...
Enric Pastor, Jordi Cortadella, Alex Kondratyev, O...
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...