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130
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DFT
1998
IEEE
78views VLSI» more  DFT 1998»
15 years 8 months ago
A System for Evaluating On-Line Testability at the RT-level
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda...
97
Voted
IFIP
1993
Springer
15 years 8 months ago
Self-Timed Architecture of a Reduced Instruction Set Computer
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...
Ilana David, Ran Ginosar, Michael Yoeli
ERSHOV
2006
Springer
15 years 8 months ago
An ASM Semantics of Token Flow in UML 2 Activity Diagrams
Abstract. The token flow semantics of UML 2 activity diagrams is formally defined using Abstract State Machines. Interruptible activity regions and multiplicity bounds for pins are...
Stefan Sarstedt, Walter Guttmann
FSE
2000
Springer
85views Cryptology» more  FSE 2000»
15 years 8 months ago
Mercy: A Fast Large Block Cipher for Disk Sector Encryption
Abstract. We discuss the special requirements imposed on the underlying cipher of systems which encrypt each sector of a disk partition independently, and demonstrate a certificati...
Paul Crowley
AMAST
2008
Springer
15 years 6 months ago
The Verification of the On-Chip COMA Cache Coherence Protocol
This paper gives a correctness proof for the on-chip COMA cache coherence protocol that supports the Microgrid of microtheaded architecture, a multi-core architecture capable of in...
Thuy Duong Vu, Li Zhang, Chris R. Jesshope