In this paper, we employ the finite state machine (FSM) model for networks to investigate fault identification using passive testing. First, we introduce the concept of passive te...
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
In this paper we brie
y describe a set of designs that can serve as examples for High Level Synthesis (HLS) systems. The designs vary in complexity from simple behavioral nite st...
Diagrams (e.g., flowcharts, trees for hierarchical structures, or graphs for finite state machines) are often needed as part of visual language systems and advanced user interfa...
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...