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149
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ANSS
2001
IEEE
15 years 8 months ago
Fault Identification in Networks by Passive Testing
In this paper, we employ the finite state machine (FSM) model for networks to investigate fault identification using passive testing. First, we introduce the concept of passive te...
Raymond E. Miller, Khaled A. Arisha
FPL
2000
Springer
124views Hardware» more  FPL 2000»
15 years 8 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
126
Voted
ISSS
1995
IEEE
109views Hardware» more  ISSS 1995»
15 years 8 months ago
1995 high level synthesis design repository
In this paper we brie y describe a set of designs that can serve as examples for High Level Synthesis (HLS) systems. The designs vary in complexity from simple behavioral nite st...
Preeti Ranjan Panda, Nikil D. Dutt
158
Voted
VL
1995
IEEE
158views Visual Languages» more  VL 1995»
15 years 8 months ago
DiaGen: A Generator for Diagram Editors Providing Direct Manipulation and Execution of Diagrams
Diagrams (e.g., flowcharts, trees for hierarchical structures, or graphs for finite state machines) are often needed as part of visual language systems and advanced user interfa...
Mark Minas, Gerhard Viehstaedt
ISQED
2010
IEEE
126views Hardware» more  ISQED 2010»
15 years 7 months ago
Modeling and verification of industrial flash memories
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...