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PTS
1993
106views Hardware» more  PTS 1993»
14 years 11 months ago
Generating Synchronizable Test Sequences Based on Finite State Machine with Distributed Ports
In the area of testing communication systems, the interfaces between systems to be tested and their testers have great impact on test generation and fault detectability. Several t...
Gang Luo, Rachida Dssouli, Gregor von Bochmann, Pa...
ICCD
1992
IEEE
126views Hardware» more  ICCD 1992»
15 years 2 months ago
High-Level State Machine Specification and Synthesis
Current synthesis methodologies based on hardwaredescription languages focus mainly on two distinct levels: behavior and register-transfer levels. In many practical cases, however...
Andreas Kuehlmann, Reinaldo A. Bergamaschi
ICCD
1993
IEEE
124views Hardware» more  ICCD 1993»
15 years 2 months ago
Synthesis of Controllers from Interval Temporal Logic Specification
for a state machine which is an abstraction for an existing sequential circuit, which can be useful for redesign or engineering change. The generated state machines can be further ...
Masahiro Fujita, Shinji Kono
FDL
2006
IEEE
15 years 4 months ago
Formalizing TLM with Communicating State Machines
Transaction Level Models are widely being used as high-level reference models during embedded systems development. High simulation speed and great modeling flexibility are the ma...
Bernhard Niemann, Christian Haubelt
ICCD
1992
IEEE
84views Hardware» more  ICCD 1992»
15 years 2 months ago
Synthesis of 3D Asynchronous State Machines
We describe a new synthesis procedure for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental m...
Kenneth Y. Yun, David L. Dill, Steven M. Nowick