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GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
15 years 2 months ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
EUROPAR
2009
Springer
15 years 2 months ago
A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor
We consider a multi-processor system-on-chip destined for streaming applications. An application is composed of one input and one output queue and in-between, several levels of ide...
Daniela Genius, Alix Munier Kordon, Khouloud Zine ...
FSEN
2009
Springer
15 years 2 months ago
Specification and Validation of Behavioural Protocols in the rCOS Modeler
The rCOS modeler implements the requirements modelling phase of a model driven component-based software engineering process. Components are specified in rCOS, a relational calculus...
Zhenbang Chen, Charles Morisset, Volker Stolz
109
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ICCTA
2007
IEEE
15 years 2 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...
ATVA
2006
Springer
158views Hardware» more  ATVA 2006»
15 years 1 months ago
Model-Based Tool-Chain Infrastructure for Automated Analysis of Embedded Systems
In many safety-critical applications of embedded systems, the system dynamics exhibits hybrid behaviors. To enable automatic analysis of these embedded systems, many analysis tools...
Hang Su, Graham Hemingway, Kai Chen, T. John Koo