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CORR
2010
Springer
120views Education» more  CORR 2010»
14 years 9 months ago
State machine models of timing and circuit design
This paper illustrates a technique for specifying the detailed timing, logical operation, and compositional circuit design of digital circuits in terms of ordinary state machines w...
Victor Yodaiken
DSRT
2008
IEEE
15 years 4 months ago
Modeling System Security Rules with Time Constraints Using Timed Extended Finite State Machines
Security and reliability are of paramount importance in designing and building real-time systems because any security failure can put the public and the environment at risk. In th...
Wissam Mallouli, Amel Mammar, Ana R. Cavalli
DAC
1991
ACM
15 years 1 months ago
A Unified Approach for the Synthesis of Self-Testable Finite State Machines
-Conventionallyself-test hardware is added after synthesis is completed. For highly sequential circuits like controllersthis design method eitherleads to high hardware overheadsor ...
Bernhard Eschermann, Hans-Joachim Wunderlich
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
15 years 1 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
TOCL
2008
113views more  TOCL 2008»
14 years 9 months ago
Abstract state machines capture parallel algorithms: Correction and extension
State Machines Capture Parallel Algorithms: Correction and Extension ANDREAS BLASS University of Michigan and YURI GUREVICH Microsoft Research We consider parallel algorithms worki...
Andreas Blass, Yuri Gurevich