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» State machine models of timing and circuit design
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TASE
2008
IEEE
14 years 10 months ago
Lean Buffering in Serial Production Lines With Nonidentical Exponential Machines
Lean buffering is the smallest buffer capacity, which is necessary and sufficient to ensure the desired production rate of a manufacturing system. Literature offers methods for des...
Shu-Yin Chiang, Alexander Hu, Semyon M. Meerkov
ATVA
2007
Springer
153views Hardware» more  ATVA 2007»
15 years 4 months ago
Continuous Petri Nets: Expressive Power and Decidability Issues
State explosion is a fundamental problem in the analysis and synthesis of discrete event systems. Continuous Petri nets can be seen as a relaxation of discrete models. The expected...
Laura Recalde, Serge Haddad, Manuel Silva
ICCD
2001
IEEE
121views Hardware» more  ICCD 2001»
15 years 7 months ago
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
Noureddine Chabini, El Mostapha Aboulhamid, Yvon S...
SAC
2005
ACM
15 years 3 months ago
Reinforcement learning agents with primary knowledge designed by analytic hierarchy process
This paper presents a novel model of reinforcement learning agents. A feature of our learning agent model is to integrate analytic hierarchy process (AHP) into a standard reinforc...
Kengo Katayama, Takahiro Koshiishi, Hiroyuki Narih...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 7 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...