1186 search results - page 109 / 238 » State machine models of timing and circuit design |
GLVLSI
2000
IEEE
15 years 2 months ago
2000
IEEE
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
DAC
2005
ACM
15 years 11 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
GLVLSI
2007
IEEE
15 years 1 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
ATAL
2007
Springer
15 years 2 months ago
2007
Springer
We contribute an approach for interactive policy learning through expert demonstration that allows an agent to actively request and effectively represent demonstration examples. I...
ISQED
2007
IEEE
15 years 4 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...