Sciweavers

1186 search results - page 10 / 238
» State machine models of timing and circuit design
Sort
View
DATE
1998
IEEE
74views Hardware» more  DATE 1998»
15 years 1 months ago
State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits
We extend the subsequence removal technique to provide signi cantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to ident...
Michael S. Hsiao, Srimat T. Chakradhar
DSD
2002
IEEE
86views Hardware» more  DSD 2002»
15 years 2 months ago
Using Formal Tools to Study Complex Circuits Behaviour
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...
Paul Amblard, Fabienne Lagnier, Michel Lévy
WSC
2000
14 years 11 months ago
Java engine for UML based hybrid state machines
One of the approaches to modeling hybrid systems is to assign algebraic-differential equations describing the continuous behavior to states of state machines that represent discre...
Andrei Borshchev, Yuri B. Kolesov, Yuri B. Seniche...
75
Voted
ICCAD
1999
IEEE
99views Hardware» more  ICCAD 1999»
15 years 1 months ago
FunState - an internal design representation for codesign
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components a...
Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Ro...
FDL
2006
IEEE
15 years 3 months ago
Formalizing TLM with Communicating State Machines
Transaction Level Models are widely being used as high-level reference models during embedded systems development. High simulation speed and great modeling flexibility are the ma...
Bernhard Niemann, Christian Haubelt