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» State machine models of timing and circuit design
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ISCA
2002
IEEE
112views Hardware» more  ISCA 2002»
15 years 2 months ago
Drowsy Caches: Simple Techniques for Reducing Leakage Power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
Krisztián Flautner, Nam Sung Kim, Steven M....
HUC
2010
Springer
14 years 8 months ago
Routine as resource for the design of learning systems
Even though the coordination of kids’ activities is largely successful, the modern dual income family still regularly experiences breakdowns in their practices. Families often r...
Scott Davidoff
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
15 years 3 months ago
Statistical static timing analysis using Markov chain Monte Carlo
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...
Yashodhan Kanoria, Subhasish Mitra, Andrea Montana...
SIGMETRICS
2002
ACM
107views Hardware» more  SIGMETRICS 2002»
14 years 9 months ago
Passage time distributions in large Markov chains
Probability distributions of response times are important in the design and analysis of transaction processing systems and computercommunication systems. We present a general tech...
Peter G. Harrison, William J. Knottenbelt
ICISC
2009
125views Cryptology» more  ICISC 2009»
14 years 7 months ago
Power Analysis of Single-Rail Storage Elements as Used in MDPL
Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic...
Amir Moradi, Thomas Eisenbarth, Axel Poschmann, Ch...