1186 search results - page 142 / 238 » State machine models of timing and circuit design |
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
In this paper, for the first time, a theory for evaluating dynamic noise margins of SRAM cells is developed analytically. The results allow predicting the transient error suscepti...
DAC
2002
ACM
15 years 11 months ago
2002
ACM
This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. Component-based design provides primitive...
DAC
2008
ACM
15 years 11 months ago
2008
ACM
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
DAC
2008
ACM
15 years 11 months ago
2008
ACM
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
ASPDAC
2000
ACM
15 years 2 months ago
2000
ACM
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...