1186 search results - page 149 / 238 » State machine models of timing and circuit design |
DAC
2008
ACM
15 years 11 months ago
2008
ACM
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
As the scale and complexity of VLSI circuits increase, Electronic Design Automation (EDA) tools become much more sophisticated and are held to increasing standards of quality. New...
ESANN
2003
14 years 11 months ago
2003
We propose an event-driven framework dedicated to the design and the simulation of networks of spiking neurons. It consists stract model of spiking neurons and an efficient event-d...
ACSAC
2005
IEEE
15 years 3 months ago
2005
IEEE
As the number of system vulnerabilities multiplies in recent years, vulnerability assessment has emerged as a powerful system security administration tool that can identify vulner...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
ion of Assembler Programs for Symbolic Worst Case Execution Time Analysis Tobias Schuele Tobias.Schuele@informatik.uni-kl.de Klaus Schneider Klaus.Schneider@informatik.uni-kl.de Re...