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» State machine models of timing and circuit design
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DAC
2005
ACM
15 years 10 months ago
Word level predicate abstraction and refinement for verifying RTL verilog
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
FSEN
2009
Springer
15 years 1 months ago
Specification and Validation of Behavioural Protocols in the rCOS Modeler
The rCOS modeler implements the requirements modelling phase of a model driven component-based software engineering process. Components are specified in rCOS, a relational calculus...
Zhenbang Chen, Charles Morisset, Volker Stolz
HASE
2008
IEEE
15 years 4 months ago
Small Logs for Transactional Services: Distinction is Much More Accurate than (Positive) Discrimination
For complex services, logging is an integral part of many middleware aspects, especially, transactions and monitoring. In the event of a failure, the log allows us to deduce the c...
Debmalya Biswas, Thomas Gazagnaire, Blaise Genest
APCCM
2009
14 years 11 months ago
Towards Accurate Conflict Detection in a VCS for Model Artifacts: A Comparison of Two Semantically Enhanced Approaches
In collaborative software development the utilization of Version Control Systems (VCSs) is a must. For this important task some graph-based VCSs for model artifacts already emerge...
Kerstin Altmanninger, Gabriele Kotsis
GECCO
2008
Springer
182views Optimization» more  GECCO 2008»
14 years 11 months ago
Avida-MDE: a digital evolution approach to generating models of adaptive software behavior
Increasingly, high-assurance applications rely on autonomic systems to respond to changes in their environment. The inherent uncertainty present in the environment of autonomic sy...
Heather Goldsby, Betty H. C. Cheng