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» State machine models of timing and circuit design
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TVLSI
2010
14 years 4 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
DAC
2005
ACM
15 years 10 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
JGAA
2006
100views more  JGAA 2006»
14 years 9 months ago
Orthogonal Hypergraph Drawing for Improved Visibility
Visualization of circuits is an important research area in electronic design automation. One commonly accepted method to visualize a circuit aligns the gates to layers and uses or...
Thomas Eschbach, Wolfgang Günther, Bernd Beck...
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
15 years 2 months ago
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
Gernot Koch, Taewhan Kim, Reiner Genevriere
DATE
2009
IEEE
178views Hardware» more  DATE 2009»
15 years 4 months ago
Correct-by-construction generation of device drivers based on RTL testbenches
Abstract—The generation of device drivers is a very time consuming and error prone activity. All the strategies proposed up to now to simplify this operation require a manual, ev...
Nicola Bombieri, Franco Fummi, Graziano Pravadelli...