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» State machine models of timing and circuit design
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ISAAC
2007
Springer
135views Algorithms» more  ISAAC 2007»
15 years 4 months ago
Fast Evaluation of Union-Intersection Expressions
Abstract. We show how to represent sets in a linear space data structure such that expressions involving unions and intersections of sets can be computed in a worst-case efficient ...
Philip Bille, Anna Pagh, Rasmus Pagh
GECCO
2008
Springer
155views Optimization» more  GECCO 2008»
14 years 11 months ago
Towards memoryless model building
Probabilistic model building methods can render difficult problems feasible by identifying and exploiting dependencies. They build a probabilistic model from the statistical prope...
David Iclanzan, Dumitru Dumitrescu
TJS
2008
95views more  TJS 2008»
14 years 9 months ago
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Akshat Verma, Sandeep Sen
95
Voted
SIGIR
2003
ACM
15 years 3 months ago
Automatic image annotation and retrieval using cross-media relevance models
Libraries have traditionally used manual image annotation for indexing and then later retrieving their image collections. However, manual image annotation is an expensive and labo...
Jiwoon Jeon, Victor Lavrenko, R. Manmatha
69
Voted
AINA
2007
IEEE
15 years 4 months ago
QOMET: A Versatile WLAN Emulator
In this paper we present the design of QOMET, the Wireless LAN (WLAN) emulator that we develop. Our approach to WLAN emulation is a versatile two-stage scenario-driven design. In ...
Razvan Beuran, Lan Tien Nguyen, Khin Thida Latt, J...