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» State machine models of timing and circuit design
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AIMS
2007
Springer
15 years 4 months ago
IBGP Confederation Provisioning
This paper proposes an optimization method for the design of large scale confederation based BGP networks. We propose a graph based model and an associated metric to evaluate the r...
Mohamed Nassar, Radu State, Olivier Festor
CVPR
2000
IEEE
15 years 11 months ago
Multisensor Integration for Building Modeling
Machine perception can benefit from the use of features extracted from data provided by a variety of sensor modalities. Recent advances in sensor design makes it possible to incor...
Andres Huertas, Zu Whan Kim, Ramakant Nevatia
TCAD
2010
88views more  TCAD 2010»
14 years 4 months ago
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
TCAD
2002
137views more  TCAD 2002»
14 years 9 months ago
Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicouple
As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these i...
Yungseon Eo, Seongkyun Shin, William R. Eisenstadt...
ATVA
2007
Springer
136views Hardware» more  ATVA 2007»
15 years 4 months ago
Symbolic Fault Tree Analysis for Reactive Systems
Fault tree analysis is a traditional and well-established technique for analyzing system design and robustness. Its purpose is to identify sets of basic events, called cut sets, wh...
Marco Bozzano, Alessandro Cimatti, Francesco Tappa...