Sciweavers

1186 search results - page 51 / 238
» State machine models of timing and circuit design
Sort
View
TCAD
2008
98views more  TCAD 2008»
14 years 9 months ago
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
Khaled R. Heloue, Farid N. Najm
IACR
2011
115views more  IACR 2011»
13 years 9 months ago
Multi-Server Oblivious RAM
Secure two-party computation protocol allows two players, Alice with secret input x and Bob with secret input y, to jointly execute an arbitrary program π(x, y) such that only th...
Steve Lu, Rafail Ostrovsky
DSD
2008
IEEE
85views Hardware» more  DSD 2008»
15 years 4 months ago
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path
Testability is one of the most important factors that are considered during design cycle along with reliability, speed, power consumption, cost and other factors important for a c...
Josef Strnadel
ASPDAC
2009
ACM
262views Hardware» more  ASPDAC 2009»
15 years 4 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...
IJCAI
2003
14 years 11 months ago
Formal Verification of Diagnosability via Symbolic Model Checking
This paper addresses the formal verification of diagnosis systems. We tackle the problem of diagnosability: given a partially observable dynamic system, and a diagnosis system obs...
Alessandro Cimatti, Charles Pecheur, Roberto Cavad...