1186 search results - page 52 / 238 » State machine models of timing and circuit design |
TCAD
2002
14 years 9 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
In this paper we address the problem of designing very high throughput finite state machines (FSMs). The presence of loops in sequential circuits prevents a straightforward and g...
WSC
1998
14 years 11 months ago
1998
Simulation at the machine-control level plays an important role in designing machine controls and operational specifications. Recently, there has been a considerable amount of wor...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
ITC
2003
IEEE
15 years 3 months ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...