1186 search results - page 61 / 238 » State machine models of timing and circuit design |
ISQED
2010
IEEE
14 years 11 months ago
2010
IEEE
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
DSN
2011
IEEE
13 years 9 months ago
2011
IEEE
In this work, we study security incidents that occurred over period of 5 years at the National Center for Supercomputing Applications at the University of Illinois. The analysis co...
ICECCS
2005
IEEE
15 years 3 months ago
2005
IEEE
When designing a complex system, Object-Z is a powerful logic-based language for modeling the system state aspects, and Timed Automata is an excellent graph-based notation for cap...
TVLSI
2010
14 years 4 months ago
2010
To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp ...
FPL
2003
Springer
15 years 3 months ago
2003
Springer
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...