1186 search results - page 64 / 238 » State machine models of timing and circuit design |
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-t...
108
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VEE
2009
ACM
2009
ACM
Post-copy based live virtual machine migration using adaptive pre-paging and dynamic self-ballooning
15 years 3 months ago
We present the design, implementation, and evaluation of post-copy based live migration for virtual machines (VMs) across a Gigabit LAN. Live migration is an indispensable feature...
100
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ICASSP
2011
IEEE
14 years 2 months ago
2011
IEEE
The Support Vector Machine (SVM) methodology is an effective, supervised, machine learning method that gives stateof-the-art performance for brain state classification from funct...
ISQED
2010
IEEE
15 years 5 months ago
2010
IEEE
— Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2...
GLVLSI
2003
IEEE
15 years 3 months ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...