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» State machine models of timing and circuit design
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TAMC
2007
Springer
15 years 4 months ago
Improving the Average Delay of Sorting
In previous work we have introduced an average-case measure for the time complexity of Boolean circuits – that is the delay between feeding the input bits into a circuit and the ...
Andreas Jakoby, Maciej Liskiewicz, Rüdiger Re...
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
15 years 4 months ago
"Green" micro-architecture and circuit co-design for ternary content addressable memory
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hw...
CCGRID
2010
IEEE
14 years 1 months ago
WORKEM: Representing and Emulating Distributed Scientific Workflow Execution State
- Scientific workflows have become an integral part of cyberinfrastructure as their computational complexity and data sizes have grown. However, the complexity of the distributed i...
Lavanya Ramakrishnan, Dennis Gannon, Beth Plale
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
15 years 2 months ago
Algorithms for Solving Boolean Satisfiability in Combinational Circuits
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
Luís Guerra e Silva, Luis Miguel Silveira, ...
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ICML
2005
IEEE
15 years 11 months ago
Finite time bounds for sampling based fitted value iteration
In this paper we consider sampling based fitted value iteration for discounted, large (possibly infinite) state space, finite action Markovian Decision Problems where only a gener...
Csaba Szepesvári, Rémi Munos