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» State machine models of timing and circuit design
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CICLING
2007
Springer
15 years 4 months ago
Finite-State Technology as a Programming Environment
Finite-state technology is considered the preferred model for representing the phonology and morphology of natural languages. The attractiveness of this technology for natural lang...
Shuly Wintner
MIDDLEWARE
2007
Springer
15 years 4 months ago
Removing the need for state dissemination in grid resource brokering
Resource brokering in Grids is nowadays handled by resource brokers that require detailed knowledge of the state of the resources that they broker. In business settings, surrender...
Peer Hasselmeyer
82
Voted
FORTE
2000
14 years 11 months ago
Systematic Performance Evaluation of Multipoint Protocols
The adventof multipoint(multicast-based) applications and the growth and complexity of the Internet has complicated network protocol design and evaluation. In this paper, we prese...
Ahmed Helmy, Sandeep K. S. Gupta, Deborah Estrin, ...
85
Voted
FATES
2004
Springer
15 years 3 months ago
Testing Deadlock-Freeness in Real-Time Systems: A Formal Approach
A Time Action Lock is a state of a Real-time system at which neither time can progress nor an action can occur. Time Action Locks are often seen as signs of errors in the model or ...
Behzad Bordbar, Kozo Okano
ICCD
2004
IEEE
172views Hardware» more  ICCD 2004»
15 years 7 months ago
A Signal Integrity Test Bed for PCB Buses
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
Jihong Ren, Mark R. Greenstreet