1186 search results - page 87 / 238 » State machine models of timing and circuit design |
80
Voted
DATE
2002
IEEE
15 years 3 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
73
Voted
ISCAS
1999
IEEE
15 years 2 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
ISPD
2010
ACM
15 years 5 months ago
2010
ACM
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
WSC
1998
14 years 11 months ago
1998
This paper presents Timed Petri Nets (TPN) as an analytical approach for verification of computerized queueing network simulation models at steady state. It introduces a generic a...
101
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EVOW
2001
Springer
15 years 2 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...