1186 search results - page 90 / 238 » State machine models of timing and circuit design |
ASYNC
2000
IEEE
15 years 2 months ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
DSN
2003
IEEE
15 years 3 months ago
2003
IEEE
This paper describes the design and evaluation of a robust integrator for software-implemented control systems. The integrator is constructed as a generic component in the Simulin...
WSC
1998
14 years 11 months ago
1998
Simulation is used to verify the feasibility of the design of manufacturing cells. The cell design, which combines new and existing machines in a component manufacture, is present...
101
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KDD
2010
ACM
15 years 2 months ago
2010
ACM
Stroke is the third leading cause of death and the principal cause of serious long-term disability in the United States. Accurate prediction of stroke is highly valuable for early...
MEMOCODE
2006
IEEE
15 years 4 months ago
2006
IEEE
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...