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» State machine models of timing and circuit design
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DAC
2005
ACM
15 years 11 months ago
Simulation models for side-channel information leaks
Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power co...
Kris Tiri, Ingrid Verbauwhede
ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
15 years 7 months ago
Practical, fast Monte Carlo statistical static timing analysis: why and how
Statistical static timing analysis (SSTA) has emerged as an essential tool for nanoscale designs. Monte Carlo methods are universally employed to validate the accuracy of the appr...
Amith Singhee, Sonia Singhal, Rob A. Rutenbar
ISCAS
2011
IEEE
278views Hardware» more  ISCAS 2011»
14 years 1 months ago
A programmable axonal propagation delay circuit for time-delay spiking neural networks
— we present an implementation of a programmable axonal propagation delay circuit which uses one first-order logdomain low-pass filter. Delays may be programmed in the 550ms rang...
Runchun Wang, Craig T. Jin, Alistair McEwan, Andr&...
ISCAS
2005
IEEE
182views Hardware» more  ISCAS 2005»
15 years 3 months ago
A new reconfigurable modem architecture for 3G multi-standard wireless communication systems
– The trend in communication systems is towards more rapidly changing specifications with shorter time intervals between updates of existing standards. This results in a coexiste...
Jung-Ho Kim, Dong Sam Ha, Jeffrey H. Reed
TASE
2009
IEEE
15 years 4 months ago
Environmental Simulation of Real-Time Systems with Nested Interrupts
Interrupts are important aspects of real-time embedded systems to handle events in time. When there exist nested interrupts in a real-time system, and an urgent interrupt is allow...
Guoqiang Li, Shoji Yuen, Masakazu Adachi