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» State machine models of timing and circuit design
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ISSS
1995
IEEE
109views Hardware» more  ISSS 1995»
15 years 1 months ago
1995 high level synthesis design repository
In this paper we brie y describe a set of designs that can serve as examples for High Level Synthesis (HLS) systems. The designs vary in complexity from simple behavioral nite st...
Preeti Ranjan Panda, Nikil D. Dutt
DT
2000
88views more  DT 2000»
14 years 10 months ago
Postsilicon Validation Methodology for Microprocessors
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...
Hemant G. Rotithor
FDL
2004
IEEE
15 years 1 months ago
A Functional Programming Framework of Heterogeneous Model of Computation for System Design
System-on-Chip (SOC) and other complex distributed hardware/software systems contain heterogeneous components such as DSPs, micro-controllers, application specific logic etc., whi...
Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shu...
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
15 years 4 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...
AIPS
1994
14 years 11 months ago
A Planner with Quality Goal and Its Speed-up Learning for Optimization Problem
Aimsof traditional planners had beenlimited to finding a sequenceof operators rather than finding an optimal or neax-optimalfinal state. Consequent]y, the performanceimprovementsy...
Masahiko Iwamoto