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» Stateful traits and their formalization
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ICSEA
2009
IEEE
14 years 10 months ago
Integrating Formal Methods with Model-Driven Engineering
In this paper, we present our position and experience on integrating formal methods with the Model-driven Engineering (MDE) approach to software development. Both these two approa...
Angelo Gargantini, Elvinia Riccobene, Patrizia Sca...
LICS
2008
IEEE
15 years 6 months ago
Hiding Local State in Direct Style: A Higher-Order Anti-Frame Rule
Separation logic involves two dual forms of modularity: local reasoning makes part of the store invisible within a static scope, whereas hiding local state makes part of the store...
François Pottier
90
Voted
CORR
2010
Springer
120views Education» more  CORR 2010»
15 years 18 days ago
State machine models of timing and circuit design
This paper illustrates a technique for specifying the detailed timing, logical operation, and compositional circuit design of digital circuits in terms of ordinary state machines w...
Victor Yodaiken
ISSRE
2002
IEEE
15 years 5 months ago
Saturation Effects in Testing of Formal Models
Formal analysis of software is a powerful analysis tool, but can be too costly. Random search of formal models can reduce that cost, but is theoretically incomplete. However, rand...
Tim Menzies, David Owen, Bojan Cukic
FM
1998
Springer
153views Formal Methods» more  FM 1998»
15 years 4 months ago
VSE: Controlling the Complexity in Formal Software Developments
We give an overview of the enhanced VSE system which is a tool to formally specify and verify systems. It provides means for structuring speci cations and it supports the developme...
Dieter Hutter, Heiko Mantel, Georg Rock, Werner St...