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DAC
2004
ACM
16 years 7 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
CORR
2010
Springer
139views Education» more  CORR 2010»
15 years 4 months ago
Centrality Metric for Dynamic Networks
Centrality is an important notion in network analysis and is used to measure the degree to which network structure contributes to the importance of a node in a network. While many...
Kristina Lerman, Rumi Ghosh, Jeon Hyung Kang
TRUSTBUS
2009
Springer
16 years 21 days ago
Operational Semantics for DKAL: Application and Analysis
DKAL is a new expressive high-level authorization language. It has been successfully tried at Microsoft which led to further improvements of the language itself. One improvement is...
Yuri Gurevich, Arnab Roy
VTS
1996
IEEE
114views Hardware» more  VTS 1996»
15 years 10 months ago
Quantitative analysis of very-low-voltage testing
Some weak static CMOS chips can be detected by testing them with a very low supply voltage -- between 2 and 2.5 times the threshold voltage Vt of the transistors. A weak chip is o...
Jonathan T.-Y. Chang, Edward J. McCluskey
RV
2010
Springer
177views Hardware» more  RV 2010»
15 years 4 months ago
Runtime Instrumentation for Precise Flow-Sensitive Type Analysis
We describe a combination of runtime information and static analysis for checking properties of complex and configurable systems. The basic idea of our approach is to 1) let the p...
Etienne Kneuss, Philippe Suter, Viktor Kuncak