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» Static performance prediction of skeletal parallel programs
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ERSA
2007
177views Hardware» more  ERSA 2007»
14 years 11 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
15 years 1 months ago
Access Region Locality for High-Bandwidth Processor Memory System Design
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
IPPS
2010
IEEE
14 years 7 months ago
On the parallelisation of MCMC by speculative chain execution
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...
97
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SPAA
2012
ACM
12 years 12 months ago
Memory-mapping support for reducer hyperobjects
hyperobjects (reducers) provide a linguistic abstraction for dynamic multithreading that allows different branches of a parallel program to maintain coordinated local views of the...
I.-Ting Angelina Lee, Aamir Shafi, Charles E. Leis...
96
Voted
ICS
2007
Tsinghua U.
15 years 3 months ago
Cooperative cache partitioning for chip multiprocessors
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a singl...
Jichuan Chang, Gurindar S. Sohi