651 search results - page 9 / 131 » Statistical Approach to NoC Design |
115
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DSD
2008
IEEE
15 years 10 months ago
2008
IEEE
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
135
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DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
126
Voted
DAC
2008
ACM
16 years 4 months ago
2008
ACM
Design-time decisions can often only cover certain scenarios and fail in efficiency when hard-to-predict system scenarios occur. This drives the development of run-time adaptive s...
160
Voted
CODES
2007
IEEE
15 years 5 months ago
2007
IEEE
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
100
Voted
DSD
2009
IEEE
15 years 10 months ago
2009
IEEE
Abstract—Pulse-based data transmission has been demonstrated as a power-saving and high performance alternative to level-based signalling over global distances. Key to its correc...