306 search results - page 12 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
73
Voted
ISMVL
1999
IEEE
15 years 4 months ago
1999
IEEE
In this paper, the theory of information relationships and relationship measures is considered and its application to logic design is discussed. This theory makes operational the ...
SBCCI
2009
ACM
15 years 4 months ago
2009
ACM
The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applicat...
75
Voted
ICCAD
2005
IEEE
15 years 8 months ago
2005
IEEE
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
120
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TMC
2012
13 years 2 months ago
2012
—This paper proposes Trajectory-based Statistical Forwarding (TSF) scheme, tailored for the multihop data delivery from infrastructure nodes (e.g., Internet access points) to mov...
PATMOS
2005
Springer
15 years 5 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...