306 search results - page 23 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
127
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ASPDAC
2006
ACM
15 years 7 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
ICCAD
2004
IEEE
15 years 10 months ago
2004
IEEE
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
131
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ANSS
2007
IEEE
15 years 8 months ago
2007
IEEE
— Delay tolerant networks (DTNs) are a class of networks that experience frequent and long-duration partitions due to sparse distribution of nodes. The topological impairments ex...
85
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DAC
2006
ACM
16 years 2 months ago
2006
ACM
Highly regular, nanodevice based architectures have been proposed to replace pure CMOS based architectures in the emerging post CMOS era. Since bottom-up self-assembly is used to ...
119
Voted
DAC
2007
ACM
16 years 2 months ago
2007
ACM
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In mos...