306 search results - page 25 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
118
Voted
FSKD
2007
Springer
15 years 3 months ago
2007
Springer
A new type of database anomaly is described by addressing the concept of Cumulated Anomaly in this paper. Dubiety-Determining Model (DDM), which is a detection model basing on sta...
ASPDAC
2008
ACM
15 years 3 months ago
2008
ACM
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
93
Voted
ICCAD
1991
IEEE
15 years 5 months ago
1991
IEEE
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
116
Voted
FPGA
2006
ACM
15 years 5 months ago
2006
ACM
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
94
Voted
IOLTS
2008
IEEE
15 years 8 months ago
2008
IEEE
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...