306 search results - page 28 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
118
Voted
CHES
2006
Springer
15 years 5 months ago
2006
Springer
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...
ISCAS
2008
IEEE
15 years 8 months ago
2008
IEEE
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
124
Voted
ICCCN
2007
IEEE
15 years 8 months ago
2007
IEEE
Abstract— This work is concerned with definining a performance index that can be used as an objective measure in the evaluation and comparison of ad hoc networking protocols. Sp...
119
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AC
2003
Springer
15 years 7 months ago
2003
Springer
Abstract. As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call...
136
Voted
MOBIHOC
2008
ACM
16 years 1 months ago
2008
ACM
The routing performance of delay tolerant networks (DTN) is highly correlated with the distribution of inter-contact times (ICT), the time period between two successive contacts o...