306 search results - page 29 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
110
Voted
DATE
2009
IEEE
15 years 8 months ago
2009
IEEE
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...
111
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ICCAD
2005
IEEE
15 years 10 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
116
Voted
WCNC
2008
IEEE
15 years 8 months ago
2008
IEEE
Packet reservation multiple access (PRMA) protocol is an implicit reservation MAC protocol. It is initially designed for voice packets in the cellular networks [2], [3] but it is...
106
Voted
ICCD
2003
IEEE
15 years 10 months ago
2003
IEEE
— We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapa...
DAC
2006
ACM
16 years 2 months ago
2006
ACM
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...