306 search results - page 30 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
109
click to vote
GPCE
2008
Springer
15 years 2 months ago
2008
Springer
A user interface, such as a dialog, assists a user in synthesising a set of values, typically parameters for a command object. Code for “command parameter synthesis” is usuall...
105
click to vote
ICCAD
1998
IEEE
15 years 6 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
115
click to vote
RTAS
2005
IEEE
15 years 7 months ago
2005
IEEE
The increasing popularity of high-volume performancecritical Internet applications calls for a scalable server design that allows meeting individual response-time guarantees. Cons...
120
Voted
ISQED
2007
IEEE
15 years 8 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
ASPDAC
2009
ACM
15 years 8 months ago
2009
ACM
In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this...