306 search results - page 31 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
102
Voted
ICCAD
1999
IEEE
15 years 6 months ago
1999
IEEE
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
111
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TSD
2004
Springer
15 years 7 months ago
2004
Springer
Abstract. This paper presents a brand-new Slovak text-to-speech system. It was developed within the framework of ARTIC system (primarily designed to synthesize Czech speech) with r...
ICCAD
2006
IEEE
15 years 10 months ago
2006
IEEE
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, th...
124
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ICCAD
2008
IEEE
15 years 10 months ago
2008
IEEE
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
118
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PATMOS
2007
Springer
15 years 8 months ago
2007
Springer
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...