306 search results - page 34 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
115
Voted
INFOCOM
2009
IEEE
15 years 8 months ago
2009
IEEE
—This paper considers the design of opportunistic packet schedulers for users sharing a time-varying wireless channel from the performance and the robustness points of view. Firs...
117
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ISQED
2009
IEEE
15 years 8 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
112
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VTS
1999
IEEE
15 years 6 months ago
1999
IEEE
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
129
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ERSA
2004
15 years 3 months ago
2004
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
124
Voted
ICCAD
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...